A method for manufacturing a memory device uses a damascene process to define memory elements. The device comprises a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A damascene patch crosses the insulating member aligned with the first and second electrodes, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided.