Memory circuits that concatenate multiple FIFOs in parallel to increase the overall depth of the memory circuits. Asymmetric input and output ports can be provided by including a deserializer on the write interface of the memory circuit and/or a serializer on the read interface of the memory circuit. The deserializer disperses the data evenly across all FIFOs, minimizing the write-to-read latency. In some embodiments, at most two of the FIFOs are active at any given time, one being written and one being read, which reduces the overall power consumption of the memory circuit compared to known structures.