A programmable activate-precharge cycle are provided for a DRAM device. Activate and precharge signals associated with the activate-precharge cycle are generated on the basis of the programmed rate and precharge time with respect to an internal clock of the DRAM device. The activate and precharge signals are coupled to wordlines of the DRAM device, and switched from one wordline to another under internal or external control. One or more functions of the DRAM device are tested while the activate and precharge signals are coupled to wordline. The manner in which switching the activate and precharge signals from one wordline to another wordline is configured depending on the type of testing to be conducted.