An information processing apparatus is provided which includes a processor for carrying out a pipeline processing over an instruction, a memory provided in the processor and input/output control means for giving access to the memory with a high priority, a memory access arranging method includes a step of causing a clock to be supplied to the processor to wait when a contention of access of the processor and the input/output control means to the memory is generated, a step of executing the access of the input/output control means to the memory, and a step of canceling the clock wait of the processor after ending the access of the input/output control means to the memory, and executing the access of the processor to the memory.