A dual damascene method of forming a metal line of a semiconductor device includes the procedures of: forming, partially annealing, etching, and cleaning. The forming procedure includes forming an SOD (spin-on dielectric) layer on an insulation layer having a contact hole to fill the contact hole. The partially annealing procedure includes annealing the SOD layer to selectively bake portions of the SOD layer which are filled in an upper portion of the contact hole and placed on the insulation layer. The etching procedure includes etching the baked portions of the SOD layer and a portion of the insulation layer to define a trench. The cleaning procedure includes cleaning the resultant structure of the trench and to remove substantially all of the unbaked portion of the SOD layer which remains in a lower portion of the contact hole.