An electronic data processing device includes a data processing member provided for controlling, based on first and second encoded data, a secured operation initiated by a user, a memory which is configurable in order to delimit at least one secured memory part within that memory, to each secured memory parts there being assigned a dedicated address range. The data processing member includes N (N.gtoreq.2) processing units of which M (M.ltoreq.N-1) processing units are provided to process the secured operation and at least one of the remaining N-M processing units is provided for processing application data, to each of the M processing units there is assigned at least one of the secured memory parts via of a configuration element controlled by a selected one of the M processing units. The second memory is provided with a memory access controller provided for controlling access to the second memory. The memory controller is provided for detecting an access request to a protected memory address, belonging to those ranges, when issued by one of a N-M processing units and for overruling a detected protected address.

 
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< Massively parallel supercomputer

> Optimized performance and power access to a shared resource in a multiclock frequency system on a chip application

> Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit

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