One embodiment of the present invention concerns a test assembly for
testing product circuitry of a product die. In one embodiment, the test
assembly includes at test die and an interconnection substrate for
electrically coupling the test die to a host controller that communicates
with the test die. The test die may be designed according to a design
methodology that includes the step of concurrently designing test
circuitry and a product circuitry in a unified design. The test circuitry
can be designed to provide a high degree of fault coverage for the
corresponding product circuitry generally without regard to the amount of
silicon area that will be required by the test circuitry. The design
methodology then partitions the unified design into the test die and the
product die. The test die includes the test circuitry and the product die
includes the product circuitry. The product and test die may then be
fabricated on separate semiconductor wafers. By partitioning the product
circuitry and test circuitry into separate die, embedded test circuitry
can be either eliminated or minimized on the product die. This will tend
to decrease the size of the product die and decrease the cost of
manufacturing the product die while maintaining a high degree of test
coverage of the product circuits within the product die. The test die can
be used to test multiple product die on one or more wafers.