ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an interpolating comparator. The interpolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.

 
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< Sliding error sampler (SES) for latency reduction in the ADC path

> Sigma-delta modulator with DAC resolution less than ADC resolution and increased tolerance of non-ideal integrators

> A/D converter, signal processor, and receiving device

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