A computer-aided hardware design system enables design of an actual hardware implementation for a digital circuit using a software implementation of an algorithm in assembly language or machine binary code by converting an algorithmic representation for a hardware design initially created in software assembly or machine binary code of a general-purpose processor, to a hardware design implementation (FPGA or ASIC) by translating software binaries or assembly code, targeted for general-purpose processors, into RTL VHDL or Verilog code to be synthesized using commercial logic synthesis and physical design tools onto FPGAs and ASICs. The system performs data flow, parallelism analysis and optimizations at the assembly and machine code level and alias analysis to analyze memory accesses and automatically identify the parallelism in the operations automatically identifying loops and other control constructs, and recognizing procedure and function calls. The system automatically generates test benches for verifying correctness of the designs.