A method of Digital to Analogue conversion of an input signal D.sub.o for suppressing the effect of clock-jitter in a Delta-Sigma analogue to digital converter, or class D amplifier, comprises charging a capacitor to a reference voltage value (V.sub.ref) during a first phase (.phi.) of a clock signal, discharging the capacitor during a second phase (.phi..sub.2) of the clock signal, wherein the discharge is regulated by a biased transistor, responsive to the voltage on the capacitor, in a first part of the second phase to provide an approximately constant discharge current, and regulated in a second part of the second phase for rapidly discharging the capacitor before the end of the second phase; and providing an output (U.sub.d, OUT) as a function of the discharge current and the input signal D.sub.o. The output signal U.sub.d, may be applied as a feedback signal to a loop filter in a Delta-Sigma converter. Alternatively, the output may represent the output of a Class D amplifier.