A semiconductor structure includes a memory cell in a first region and a logic MOS device in a second region of a semiconductor substrate. The memory cell includes a first gate electrode over the semiconductor substrate; a first gate spacer on a sidewall of the first gate electrode, wherein the first gate spacer comprises a storage on a tunneling layer; and a first lightly-doped source or drain (LDD) region and a first pocket region adjacent to the first gate electrode. The logic MOS device includes a second gate electrode on the semiconductor substrate; a second gate spacer on a sidewall of the second gate electrode; a second LDD region and a second pocket region adjacent the second gate electrode, wherein at least one of the first LDD region and the first pocket region has a higher impurity concentration than a impurity concentration of the respective second LDD region and the second pocket region.