A memory system is provided that supports partial cache line write
operations to a memory module to reduce write data traffic on a memory
channel. The memory system comprises a memory hub device integrated in
the memory module and a set of memory devices coupled to the memory hub
device. The memory hub device comprises burst logic integrated in the
memory hub device. The burst logic determines an amount of write data to
be transmitted to the set of memory devices and generates a burst length
field corresponding to the amount of write data. The memory hub also
comprises a memory hub controller integrated in the memory hub device.
The memory hub controller controls the amount of write data that is
transmitted using the burst length field. The memory hub device transmits
the amount of write data that is equal to or less than a conventional
data burst amount.