An apparatus and method for executing a Load Register instruction in which
the source data of the Load Register instruction is retained in its
original physical register while the architected target register is
mapped to this same physical target register. In this state the two
architected registers alias to one physical register. When the source
register of the Load Address instruction is specified as the target
address of a subsequent instruction, a free physical register is assigned
to the Load Registers source register. And with this assignment the alias
is thus broken. Similarly when the target register of the Load Address
instruction is the target address of a subsequent instruction, a new
physical register is assigned to the Load Registers target address. And
with this assignment the alias is thus broken.