A processor that can execute instructions in either scalar mode or vector
mode. In scalar mode, instructions are executed once per fetch. In vector
mode, instructions are executed multiple times per fetch. In vector mode,
the processor recognizes scalar variables and vector variables. Scalar
variables may be assigned a fixed memory location. Vector variables use
different physical locations at different iterations of the same
instruction. The processor includes circuitry to automatically index
addresses of vector variables for each iteration of the same instruction.
This circuitry partitions a register into a vector region and a scalar
region. Accesses to the vector region are automatically indexed based on
the number of iterations of the instruction that have been performed.