In some aspects, a method of fabricating a memory cell is provided that
includes: (1) fabricating a first conductor above a substrate; (2)
selectively fabricating a carbon nano-tube ("CNT") material above the
first conductor by: (a) fabricating a CNT seeding layer on the first
conductor, wherein the CNT seeding layer comprises silicon-germanium
("Si/Ge"), (b) planarizing a surface of the deposited CNT seeding layer,
and (c) selectively fabricating CNT material on the CNT seeding layer;
(3) fabricating a diode above the CNT material; and (4) fabricating a
second conductor above the diode. Numerous other aspects are provided.