A system and method for communicating between graphical programs executing on respective devices, e.g., a programmable hardware element and a controller. The system includes a first node representing a direct memory access structure, e.g., a first in, first out data structure (DMA FIFO), and a second node providing a controller interface to the DMA FIFO. A first portion of the DMA FIFO is implemented on the programmable hardware element, and a second portion of the DMA FIFO is implemented in memory of the controller. The first and second nodes are operable to be included respectively in first and second graphical programs, where the first graphical program, including the first node, is deployable to the programmable hardware element, where the second graphical program, including the second node, is deployable to the controller, and where the first and second graphical programs communicate via the DMA FIFO in cooperatively performing a specified task.