A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller. The first two-on-one link is coupled to the first port of the buffer device. The first memory subsystem is configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device. The first two-on-one link includes up to two transceivers connected to a single link, with at least one of the up to two transceivers consisting of any one of two or more transmitters for transmitting signals or two or more receivers for receiving signals.