A source driving circuit includes a shift register, a data latch circuit, a D/A converter, and a sample-and-hold circuit. The shift register generates an n-bit first signal in response to a clock signal and an input/output control signal, wherein n is a positive integer. The data latch circuit samples video data using the first signal to latch the sampled video data, and outputs 3.times.n digital signals. The D/A converter generates a plurality of analog voltage signals corresponding to the 3.times.n digital signals using a plurality of gray scale voltages. The sample-and-hold circuit generates 6.times.n sample-and-hold signals using the analog voltage signals in response to a plurality of switching control signals.