In one embodiment taught herein, a memory module selectively uses its write data mask input as a status output on which it provides status signaling to an associated memory controller. The memory module configures its data mask input as a status output at one or more times not conflicting with write operations. Correspondingly, the memory controller configures its write data mask output as a status input at such times, for receipt of status signaling from the memory module. In one embodiment, the memory module maintains a status register related to one or more operating conditions of the module, such as temperature, and signals status information changes to the memory controller by driving the module's data mask input. In response to such signaling, the memory controller initiates a read of the module's status register to obtain updated status information, and takes appropriate action, such as by changing the module's refresh rate.