A semiconductor memory having two different memory areas in one chip includes a memory cell array including a first variable memory area controlled to be accessible in at least first and second operation modes, and a second variable memory area controlled to be inaccessible in one of the first and second operation modes; and a memory control unit for storing area information discriminating between the first memory area and the second memory area and generating memory control signals for controlling access to the first memory area and the second memory area. One memory can be substituted for a memory combination including ROMs and RAMs in one chip.