A circuit system is provided capable of improving the throughput thereof by eliminating the operational constraint that if the operating frequency of a content addressable memory is lower than the operating frequency of a system LSI, two system clocks should be provided, or the higher frequency should be synchronized with the slower system clock. A clock control circuit (103) for down-converting an internal clock (.PHI.1) of a LSI (101) is provided, and a control signal whose frequency is made lower is used to operate a content addressable memory circuit (102).