A receiver arrangement including a received data reproducing device
includes an RF (Radio Frequency) receiver configured to determine the
signal strength of a received signal and feed it to a clock frequency
determining circuit. Number-of-error information, included in the outputs
of a clock phase detector and produced during error detection effected
with a sync word, a packet header and a payload of a packet field by
field, are also fed to the clock frequency determining circuit. The clock
frequency determining circuit designates a subject to deal with the
packet and selects single clock frequency information out of clock
frequencies determined. The clock frequency information thus selected is
input to the clock phase detector.