The invention relates to a phase locked loop or "PLL" (12) and a method for the operation of a PLL (12), wherein a controllable oscillator (DCO) generates an output signal (CKout) and can be switched over between a first clock signal (CKin1 or CKin2) and a second clock signal (CKin2 or CKin1) for use as the input clock signal of the PLL (12). According to the invention, for the clock signal (CKin1 or CKin2) currently being used to generate the output signal (CKout), a phase difference between this clock signal and the output signal (CKout) is determined and used for the control of the oscillator (DCO), whereas for the clock signal (CKin2 or CKin1) currently not being used to generate the output signal (CKout), its frequency difference with respect to the output signal (CKout) is determined and stored and continuously updated and provided for the control of the oscillator (DCO) after the switch-over to this clock signal previously not being used. The PLL output signal (CKout) can thus follow more quickly any switch-over-related frequency change of the clock signal being used.