The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.

 
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> Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations

> Method and computer program product for interlayer connection of arbitrarily complex shapes under asymmetric via enclosure rules

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