A memory system for providing a slow command decode over an untrained high-speed interface. The memory system includes a memory system having a memory interface device, an untrained high-speed interface, and a memory controller. The untrained high-speed interface is in communication with the memory interface device. The memory controller generates slow commands and transmits the slow commands to the memory interface device via the untrained high-speed interface. The slow commands operate at a first data rate that is slower than a second data rate utilized by the high-speed interface after it has been trained. The memory interface device receives the slow commands via the untrained high-speed interface, decodes the slow commands, and executes the slow commands.