A clock synchronization buffer for a counter clock flow pipelined circuit
including a cascade of processing modules that receive data from a
previous module and provide output results to a following module. The
clock synchronization buffer receives a clock input signal and provides
clock signals to a local processing module and to the next pipeline
stage. The clock synchronization buffer includes a selectable delay stage
that receives a clock input signal and a delay select signal and outputs
a clock signal having a selected delay. An amplifier connected to the
selectable delay stage provides the delayed clock signal to a local
processing module that corresponds to the clock synchronization buffer
circuit. An inverting amplifier connected to the selectable delay stage
provides the delayed clock signal to the next pipeline stage. A clock
synchronization controller synchronizes the phases of reference clock
input and synchronized clock input signals.