An instruction processing circuit includes an instruction decoder, with an
instruction input coupled to an instruction source and a control output
coupled to the control input of an execution circuit. The instruction
decoder includes a predecoding circuit, multiple freezing circuits and
multiple sub-decoding circuits. The predecoding circuit has an input
coupled to the instruction input and outputs coupled to control inputs of
the freezing circuits, which feed the respective parallel sub-decoding
circuits. The predecoding circuit detects to which type of instruction a
supplied instruction belongs, and controls, dependent on the detected
type, to which of the sub-decoding circuits instruction information
derived from the supplied instruction will be passed and to which of the
sub-decoding circuits supply of instruction information derived from a
previously supplied instruction will be frozen.