A modulo arithmetic (61) for generating the addresses for accessing the memory cells of a memory in a DSP (digital signal processor) includes three inputs: an input address (30), an increment (31) and a modulo value (33). The next address (36) is generated based on these inputs as follows. An adder (22) generates a first address (32) by adding the input address (30) and the increment (31) and a second address (34) is generated by subtracting the modulo (33) from the first address (32) by means of the subtractor (23). The comparator (45) checks whether the second address is lower than or equal to zero and if so, the multiplexer (24) outputs the first address at its output (36). If the second address is higher than zero, the multiplexer (24) is controlled such that it outputs the second address (34). A further comparator (63) compares the input address (30) and the modulo (33). If the input address (30) is different from the modulo (33), the multiplexer (64) generates the next output address (66) by selecting the output (36) of the multiplexer (24) and if the input address (30) is equal to the modulo (33) the multiplexer (64) generates the next output address (66) by selecting the constant value "0" (67) inputted at a second input of the multiplexer (64). This modulo arithmetic allows to directly and repeatedly access the elements of a matrix stored in a digital memory row by row in a direction of its columns.