A vertical thin film transistor (TFT) structure allows for a channel length to be scaled down, below that allowed by lateral TFT structures, to nanoscale (i.e., below 100 nm). However, while reducing the channel length, short-channel effects have been found in previous VTFT structures. Aspects of the new vertical TFT structure allow for the suppression of some of the short-channel effects. Advantageously, the capability of defining nanoscale channel length with short-channel effect suppression allows for p-channel vertical TFTs, where previously these were impractical. Furthermore, in aspects of the vertical TFT structure, the gate electrode is entirely vertical and by eliminating the horizontal overlap of the gate electrode over the drain electrode that present in earlier vertical TFT structures, parasitic gate-to-drain capacitance is eliminated. The vertical TFT structure provides size advantages over lateral TFTs and, furthermore, allows a TFT to be built at the intersection of electrode lines in an active-matrix configuration.