Methods and apparatus are provided. A memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer gate, and a second bit line selectively coupled to the input of the sensing device through a second multiplexer gate. The first bit line is formed at a first vertical layer and is coupled to a first source/drain region of the first multiplexer gate. The input of the sensing device is formed at a second vertical layer different than the first vertical layer and is coupled to a second source/drain region of the first multiplexer gate and a first source/drain region of the second multiplexer gate. The second bit line is formed at the first vertical layer and is coupled to a second source/drain region of the second multiplexer gate.