A memory array comprising array lines of first and second types coupled to
memory cells includes a first hierarchical decoder circuit for decoding
address information and selecting one or more array lines of the first
type. The first hierarchical decoder circuit includes at least two
hierarchical levels of multi-headed decoder circuits. The first
hierarchical decoder circuit may include a first-level decoder circuit
for decoding a plurality of address signal inputs and generating a
plurality of first-level decoded outputs, a plurality of second-level
multi-headed decoder circuits, each respective one coupled to a
respective first-level decoded output, each for providing a respective
plurality of second-level decoded outputs, and a plurality of third-level
multi-headed decoder circuits, each respective one coupled to a
respective second-level decoded output, each for providing a respective
plurality of third-level decoded outputs coupled to the memory array.