A data bus sense amplifier circuit can include a first sense amplifier block configured to provide first amplified signals by sensing inputted signals, a second sense amplifier block configured to provide second amplified signals by sensing the first amplified signals, and a sense amplifier control unit configured to provide first and second enable signals which control activations of the first and second sense amplifier blocks, respectively, wherein the sense amplifier control unit controls the first enable signal to be synchronized with the second enable signal so that the first enable signal is inactivated.