Disclosed is a wireless communication system, more particularly, a
receiver and a chipset for DSRC. A receiver includes: a low noise
amplifier (LNA) amplifying a received radio (RF) signal while minimizing
amplification of noise included in the received RF signal; a mixer
down-converting a frequency of an output signal of the LNA to output an
intermediate frequency (IF) signal; a frequency synthesizer generating
and outputting a frequency signal for the frequency-down conversion of
the mixer to the mixer; a bandpass filter passing a necessary band of a
channel in an output signal of the mixer; a log amplifier amplifying an
output signal of the bandpass filter in log scale and outputting a
received signal strength indicator of an output signal of the bandpass
filter; a detector comparing an output of the log amplifier with a
predetermined binary threshold value, outputting a first binary signal
when the output of the log amplifier is less than the predetermined
binary threshold value, and outputting a second binary signal when the
output of the log amplifier is equal to or greater than the predetermined
binary threshold value; a switch serially connected with an output
terminal of the detector; and a switch controller comparing the received
signal strength indicator of the output signal of the log amplifier with
an RSSI threshold, opening the switch when the received signal strength
indicator is less than the RSSI threshold, and closing the switch when
the received signal strength indicator is equal to or grater than the
RSSI threshold.