Embodiments of the present invention relate to methods and devices where
an erase count is maintained for at least one block of solid state
memory. Errors are corrected in data read from the solid state memory in
accordance with the associated erase count of the memory block. In some
embodiments, one or more of the following error-correction operations may
be effected according to the associated erase count of a memory block
from which the data is read: (i) a decoder and/or decoder mode is
selected; (ii) a decision to attempt correcting errors using a
lighter-weight weight decoder (mode) and/or heavier weight decoder (mode)
and/or faster decoder (mode) and/or slower decoder (mode) is made; (iii)
a mode transition and/or error correction attempt resource budget is
determined; (iv) a number of soft bits is determined; and (v) a decoding
bus width size is selected.