Provided is a test mode control circuit capable of preventing an MRS (mode
register set) from changing in a test mode exit after a test mode entry.
In the test mode control circuit, an MRS controller logically combines an
MRS signal, a bank address, an MRS address, and a test mode control
signal to output a latch control signal. A test mode control unit detects
a test mode entry and a test mode exit to selectively activate one of a
test mode set signal and a test mode exit signal, and outputs the test
mode control signal having different voltage levels according to an
activation state of the test mode set signal or the test mode exit
signal. An address latch latches an input address when the MRS signal is
activated, and outputs the latched input address as the MRS address when
the latch control signal is activated.