A stack package may have a plurality of unit packages. Each unit package may include a first substrate, a semiconductor chip, and a second substrate. Conductive supports may stack the second substrate on the first substrate. Conductive bumps may be provided on the bottom surface of the first substrate. An encapsulant may seal the semiconductor chip exposing the top surface of the second substrate. The conductive bumps of an upper unit package may be connected to the second substrate of the lower unit package.