A clock gater includes a first logic circuit that receives an enable signal and that includes first and second subcircuits. The clock gater also includes a latch that shares first and second nodes with the first logic circuit and that includes third and fourth subcircuits. The first logic circuit and the latch receive a clock signal that varies between first and second clock states. The first and third subcircuits pull the first and second nodes, respectively, to a common precharge voltage based on the first clock state in order to pass the clock signal. The second and fourth subcircuits pull the first and second nodes, respectively, to complementary voltages based on the second clock state to pass the clock signal. The first node passes the clock signal or gates the clock signal based on the enable signal.