A system and method for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an IC design which tests a set of dummy devices that are identical to a selected set of devices contained in the IC. The device test structures are selected from a library according to customer requirements and design requirements. The selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design to be manufactured.