A processor is provided that includes inputs to receive headers and payloads of messages in block form, a cipher key, a counter block, and an indication that a data block is ready to be received at the processor's first input, and that outputs a data block processes according to a CCM protocol and a signal requesting the provision of a data block at the processor input. The processor also includes first and second cipher circuits generating ciphered results that are a function of a input data block and an input cipher key. Furthermore, the processor includes a controller that processes a first sequence of data blocks through the first cipher circuit to generate a message integrity code and a second sequence of data blocks through the second cipher circuit to generate a set of ciphered data blocks.