An interface device (D) is dedicated to debugging and/or tracing in a computer system (CS) comprising at least one master (M1, M2, M3) working with at least one slave (SLj) adapted to be readable and writable at chosen addresses, each master being adapted to execute tasks and to deliver slave addresses for reading and/or writing purposes. This interface device (D) comprises i) a group of first FIFO memories (SMi) each assigned to one master for storing data representative of the tasks it executes, ii) a group of dynamically allocatable second FIFO memories (DFk) linkable to one another and to the first FIFO memories (SFi), and iii) processing means (PM) arranged to compute dynamically the FIFO memory size required by each master at a given time, considering the tasks it is executing, and to allocate dynamically a number of second FIFO memories (DFk) to each master chosen according to the corresponding computed FIFO memory size.