A clock circuit for an integrated circuit having at least one MOS transistor. The clock circuit includes a first circuit for inducing a degradation of the transistor as a function of time and circuit for measuring a parameter of the transistor that reflects a lowering of the performance of the transistor resulting from the degradation. This also includes a method of generating a counting value of clock circuit by inducing continuous degradation of an MOS transistor. The method could include measuring a parameter of transistor, reflecting a lowering of performance of transistor resulting from the degradation. The method could also include measuring the temperature and calculating the counting value of the clock from the value of the parameter, from the measured temperature and from a law of variation of the parameter as a function of time and temperature.