A multiplier-accumulator (MAC) block can be programmed to operate in one
or more modes. When the MAC block implements at least one
multiply-and-accumulate operation, the accumulator value can be zeroed
without introducing clock latency or initialized in one clock cycle. To
zero the accumulator value, the most significant bits (MSBs) of data
representing zero can be input to the MAC block and sent directly to the
add-subtract-accumulate unit. Alternatively, dedicated configuration bits
can be set to clear the contents of a pipeline register for input to the
add-subtract-accumulate unit.