When a concentration of access requests on a specific bank occurs, the delay time is caused due to the competition among the accesses, thereby lowering the processing speed of an information processing apparatus as a whole. A data transfer arbitration unit 172 sequentially transfers data to be recorded to a memory controller 160 that records data in memory having a plurality of banks. A selector 174 selects any DMAC 170 from among a plurality of DMACs, irrespective of priority sequence of transfer service for the DMAC. A transmitter 176 transmits, to a control-side transfer unit 114, data requested to be transferred by the selected DMAC 170. The selector 174 selects consecutively the DMAC 170 so that the transfer service for the same DMAC is consecutively executed, and determines the number of consecutive selections so that a transfer across the banks of the DMAC 170 occurs by a plurality of the transfer services.