DFM systems are provided that incorporate manufacturing variations in the
analysis of integrated circuits by calculating predicted manufacturing
variations on the shapes of interconnects and devices of the drawn layout
of a circuit design. The shape variation on interconnects is converted to
variations in resistor-capacitor (RC) parasitics. The shape variation on
devices is converted to variations in device parameters. The variation in
device parameters and wire parasitics is converted to changes in timing
performance, signal integrity, and power consumption by determining the
impact of device parameter and wire parasitic variations on the behavior
of each instance of a standard cell. The results from these analyses are
integrated back into the design flow as incremental delay files (timing),
noise failures and buffer insertion/driver resizing commands (noise), and
leakage power hotspots and cell substitution commands (power
consumption).