Disclosed is a synchronous semiconductor device including clock generation circuit that frequency divides a clock signal (PCLK) input from an input buffer and generates first and second internal clock signals having a predetermined phase difference from first and second frequency-divided clock signals of different phases, respectively, a first input circuit control unit that receives a chip select signal and samples the chip select signal in synchronization with the clock signal, second and third input circuit control units that sample an output of the first input circuit control unit in synchronization with the first and second internal clock signals, respectively, and first and second input circuits that receive a result of a logic operation between the output of the first input control unit and an output of the second input circuit control unit and a result of a logic operation between the output of the first input circuit control unit and an output of the third input circuit control unit as input enable signals, respectively, and sample an externally input signal in synchronization with the first and second internal clock signals, respectively based on enabling instructed by the input enable signals.