A memory cell array including a data line; a capacitor; and a transistor
coupled between the data line and the capacitor. At least one of the
capacitor and the transistor includes a material with a mutable
electrical characteristic.A memory cell array including a first
transistor coupled between a first node, a second node, and a third node;
and a second transistor coupled between the second node and a fourth
node. The first transistor includes a material with a mutable electrical
characteristic.