An instruction used by a processor in a determination of whether to perform a trap is disclosed. The instruction includes a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value used in the determination. The determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access. The determination is based at least in part on more than one of the following: a group of one or more marker bits included in the first address value, a matrix entry located at least in part using one or more bits of the first address value, a Translation Look-aside Buffer entry associated with the first address value, whether the first address value is associated with stack allocated memory, and whether the first address value includes a null value.