An apparatus and method for compensating for asymmetric write current in a
non-volatile unit cell. The unit cell comprises a switching device and an
asymmetric resistive sense element (RSE), such as an asymmetric resistive
random access memory (RRAM) element or an asymmetric spin-torque transfer
random access memory (STRAM) element. The RSE is physically oriented
within the unit cell relative to the switching device such that a hard
direction for programming the RSE is aligned with an easy direction of
programming the unit cell, and an easy direction for programming the RSE
is aligned with a hard direction for programming the unit cell.