An asynchronous adder permits asynchronous design in which dual-rail
encoding is employed, not only for a control part but also for a datapath
part including an ALU. An asynchronous adder of an exemplary embodiment
includes a combinational circuit to perform full addition with, as an
input value, an addend X, an augend Y and a carry-in C.sub.in that are
dual-rail encoded, and to output a sum output Z and a carry output
C.sub.out that are dual-rail encoded as an output value.