A computing system may comprise a processor and a memory controller hub coupled by an external bus such as the front side bus. The processor may also comprise a cache. The processor may operate in SMM and the memory coupled to the memory controller hub may comprise SMM spaces such as compatible, HSEG, and TSEG areas. A software-based attack may write malicious instructions into the cache at an address corresponding to the SMM spaces. The illegal processor memory accesses that occur entirely inside the processor caches due to the cache attack may be forced to occur on the external bus. The memory controller hub may be capable of handling the memory accesses occurring on the external bus thus, protecting the SMM spaces against cache attack.